FPGA group in Synopsys delivers a number of products such as Synplify Pro, Synplify Premier, ProtoCompiler, Certify and Identify. These products are widely used in the industry for implementation of FPGA designs, prototyping and debugging of ASICs using FPGAs. Logic synthesis software, which is part of Synplify Pro and Synplify Premier products, is the industry standards for producing high[1]performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Looking for a Senior R&D engineer in ProtoCompiler R&D with a specialization in Static Timing Analysis to join our team in Sunnyvale/Marlborough.
Roles and responsibilities include:
- Designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for Prototyping from RTL to FPGA bit stream generation.
- RTL compilation & optimization, partitioning designing, timing analysis for inter and intra-FPGA paths, technology mapping, logic and timing optimization steps.
- Write requirement and functional specifications, design and implement efficient data structures and algorithms in C/C++.
- Incorporate advanced software engineering tools and processes related to documentation and coding practices, memory and runtime profiling, coverage, unit testing in the development process.
- Work with CAE team in test planning, execution and customer support.
- Maintain and support existing product and features.
- Work in large and complex design automation environment.
Requirements:
- Bachelors/masters in CS/EE from a recognized university.
- 8+ years of experience in designing, developing and maintaining large EDA software.
- Solid background in digital logic design.
- Expertise in data structures, graph algorithms and C/C++ programming on Windows/Unix.
- Good familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis.
- Working knowledge of FPGA prototyping, design tools and flows.
- Experience with tools such as gprof, purify, coverity etc
- Sound problem solving skills
In addition, the following are highly desirable:
- Strong knowledge of Static Timing Analysis including handling of clocks and clock behaviour
- Graph theory
- Algorithms
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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